HEVC Hardware Decoder Implementation for UHD Video Applications

In this paper, an efficient hardware architecture that exploits parallel processing for HEVC decoders is proposed by introducing (i) a Coding Tree Unit (CTU)-level pipelined architecture for single-core based processing; and (ii) a multi-core based parallel processing architecture for picture partition decoding with low latency while not requiring additional resources for in-loop filtering (ILF) for neighboring samples of picture partition boundaries. The proposed parallel processing hardware architecture of HEVC decoders is especially effective for UHD video coding where excessive amount of input data inevitably requires a parallel processing architecture for realtime applications. In order to show the effectiveness of the decoder architecture, a dual-core HEVC decoder implementation is tested on a prototyping FPGA board that is available for public demonstration. The decoder design is estimated to be capable of real-time decoding for 4K/8K-UHD bitstreams when implemented on a SoC.